1. Field of the Invention
The present invention relates to a data-driven information processing device. In particular, the present invention relates to data-driven information processing device and method with an improved processing rate for a data packet including a plurality of data.
2. Description of the Background Art
In recent years, there has been a growing demand for improvement of the performance of a processor in various fields like the fields of multimedia processing and high-definition image processing, for example, which require fast processing of a large volume of data. With the current LSI (large-scale integrated circuit) manufacturing technique, however, there is a limit to the increase of the speed of devices. Attention is then focused on parallel processing that is now studied and developed seriously.
Attention is drawn to computer architectures applied to parallel processing, in particular, to data-driven architecture. According to the data-driven processing architecture, parallel processing is carried out following a rule “if all of the input data necessary for certain processing are ready and such resources as operation unit required for the processing are allocated, that processing is executed.”
The applicant of the present application discloses in Japanese Patent Laying-Open No. 9-114664 a data-driven information processing device processing a data packet including a plurality of data. FIG. 1 shows a structure of a data packet processed by this conventional data-driven information processing device. The data packet includes a tag section 101 and a data section 102. Tag section 101 includes destination information 103 indicating a node number in a program, instruction information 104 indicating any type of arithmetic operation to be performed on a plurality of data included in data section 102, and effective data information 105 indicating which of the multiple data included in data section 102 is effective. Data section 102 includes data 0 (106) and data 1 (107).
FIG. 2 is a block diagram schematically showing a configuration of a data-driven processor processing the data packet as shown in FIG. 1. The data-driven processor includes a junction unit 201, a firing control unit 202, a memory control unit 203, an operation unit 204, a program storage unit 205 and a branch unit 206. A plurality of data-driven processors of this type are connected in parallel to constitute a data-driven information processing device.
Junction unit 201 conducts arbitration of input between a data packet supplied from an input control unit (not shown) and a data packet supplied from branch unit 206 to provide these data packets to firing control unit 202 by arranging the data packets in order so as not to cause conflict therebetween.
For each data slot in the supplied data packet, firing control unit 202 determines whether or not there is an address for data to be subjected to operation (address at which the data to be subjected to operation is stored) in a queuing memory (not shown). If the supplied data packet and for each slot the address of data to be subjected to operation are present in the queuing memory, firing control unit 202 generates a data packet as shown in FIG. 1 from these data addresses and outputs the generated data packet to memory control unit 203. If the supplied data packet and any of the addresses for the data to be subjected to operation (address at which the data to be subjected to operation is stored) are absent in the queuing memory, firing control unit 202 stores the data in the queuing memory to wait for data addresses.
If data 0 (106) and data 1 (107) indicate respective addresses in a table memory (not shown), memory control unit 203 accesses the table memory to obtain the data values to be subjected to operation and generate a data packet including the data values.
Operation unit 204 refers to instruction information 104 to perform such operation as multiplication and addition on the data included in the data packet generated by firing control unit 202 or memory control unit 203 and provides the result of the operation to program storage unit 205.
Program storage unit 205 receives the result of the operation from operation unit 204 to generate a data packet having exchanged destination information 103 necessary for fetch of a next instruction and instruction information 104 and output the generated data packet to branch unit 206.
Branch unit 206 refers to destination information 103 in the data packet supplied from program storage unit 205 and, if branch unit 206 determines that the data should be processed in its own data-driven processor, branch unit 206 outputs the data packet to junction unit 201. If branch unit 206 determines that the data should not be processed in the own data-driven processor, branch unit 206 provides the data packet to another data-driven processor.
FIG. 3 is a block diagram showing details of memory control unit 203 in FIG. 2. Memory control unit 203 includes a packet copy unit 301, an address calculation unit 302, a memory access unit 303 and a packet reconstruction unit 304.
If the data included in the data packet indicate addresses in the table memory, packet copy unit 301 refers to effective data information 105 to determine if data 0 (106) and data 1 (107) are effective. If the two data in data section 102 are effective, packet copy unit 301 copies the data packet to generate a first packet for data 0 (106) and a second packet for data 1 (107).
Address calculation unit 302 refers to data 0 (106) included in the first packet to perform address calculation. Memory access unit 303 accesses the table memory according to the address calculated by address calculation unit 302 to obtain data corresponding to the first packet.
Similarly, address calculation unit 302 refers to data 1 (107) included in the second packet to perform address calculation. Memory access unit 303 accesses the table memory according to the address calculated by address calculation unit 302 to obtain data corresponding to the second packet.
Packet reconstruction unit 304 generates a new data packet by incorporating therein these two data obtained by memory access unit 303. For example, packet reconstruction unit 304 writes the obtained data corresponding to the first packet in a data region of data 0 in the first packet, and writes the obtained data corresponding to the second packet in a data region of data 1 to generate the new data packet.
As for the conventional data-driven information processing device as discussed above, if two data included in the data packet indicate address information of the table memory, memory access unit 303 accesses the table memory according to the address information for each data, resulting in a problem that two cycles are required and the throughput of the entire data-driven information processing device is accordingly decreased. This problem becomes serious as the number of data included in the data packet increases. Moreover, a similar problem occurs when memory access unit 303 writes the data stored in the data packet into the table memory.